1. Field of the Invention
The present invention relates to telephone systems, and particularly to circuit arrangements for time-division multiplex telecommunication switching systems, particularly for pulse code modulation (PCM) telephone switching systems. More particularly, the invention relates to such systems having a time-division multiplex switching network by way of which, in comparison to a connection (single channel connections) loading only a respective single time channel, connections loading two or more time channels (multi-channel connections) can be produced for the purpose of attaining greater bandwidth and/or a finer amplification gradation, and in which, given the switching of time channels of an incoming time-division multiplex line belonging to a multi-channel connection to corresponding time channels of an outgoing time-division multiplex line by means of a full memory suitable for the acceptance of the partial information maximally transmittable in pulse frame, the original chronological sequence of the partial information incoming per pulse frame via the time channels is retained upon their transmission, and in which the write operation serves for an acceptance of the incoming partial information at memory locations of the full memory only per incoming time channel is cyclically executed and the read operation which serves for a relaying of the partial information only via the outgoing time channels is executed according to switching data which indicate the allocation of the outgoing time channels to the incoming time channels and are stored per outgoing time channel at memory locations of a holding memory in the form of memory location addresses of the full memory.
2. Description of the Prior Art
A circuit arrangement of the type generally set forth above is already known from the German allowed and published application 2,246,534 which corresponds to the British patent specification No. 1,417,300. The interrelationships and details of the reasons for a production of multi-channel connections are likewise known in the art. The circuit arrangement disclosed in the aforementioned application and patent, because of the employment of a full memory in the completion of not only single-channel connections, but of multi-channel connections as well, makes relatively complicated and, therefore, work-intensive counting, linkage and selection operations necessary for the exchange-oriented assignment of free outgoing time channels to incoming busy time channels of a multi-channel connection to be completed.
Furthermore, the known arrangement proceeds from the fact that the pulse frame boundaries of the write pulse frames, read pulse frames and the pulse frames of the incoming and the outgoing time-division multiplex lines chronologically coincide. Given a multi-stage switching matrix network having a plurality of time slot multiple switching matrix stages, the partial information transmitted via the time channels nonetheless experience a delay which is caused by the write operations and read operations and the serial-to-parallel conversions and parallel-to-serial conversions which occur, the delay adding up from switching matrix stage (time slot multiple)-to-switching matrix stage.
Therefore, it has been provided in known time-division multiplex switching matrix networks to differently drive the time slot multiples of the various switching matrix stages in such a manner that the right pulse frames and read pulse frames are not coincident from coupling matrix stage-to-coupling matrix stage with respect to the pulse frame boundaries but, rather, that the pulse frame boundaries are mutually offset so that the write pulse and read pulse boundaries are chronologically matched to the pulse frame boundaries of the pulse frame of the time-division multiplex lines. As proceeds from the above explanations, the pulse frames of the time-division multiplex lines, of course, which extend between the various switching matrix stages, are not chronologically coincident with respect to the pulse frame boundaries, depending upon the two switching matrix stages between which they respectively extend. In that the time multiples of the different switching matrix stages in known time-division multiplex switching systems are controlled in such a manner that the pulse frames are respectively chronologically matched with respect to the pulse frame boundaries to the pulse frame boundaries of the pulse frames of the incoming time-division multiplex lines, sequence problems for the successive partial information of a multi-channel connection are avoided in this case which is well known in the art. However, a control condition by the chronological matching which is not isochronic with respect to the pulse frame boundaries for all time slot multiple switching matrix stages results in the fact that the control operations become more involved, particularly in view of the work expense and in view of the switching means serving the control.